1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits. More particularly, the invention relates to a process for depositing a hard mask on a dielectric layer and structures which include the hard mask and the dielectric layer.
2. Description of the Related Art
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore""s Law), which means that the number of devices that will fit on a chip doubles every two years. Today""s fabrication plants are routinely producing devices having 0.35 xcexcm and even 0.18 xcexcm feature sizes, and tomorrow""s plants soon will be producing devices having even smaller geometries.
To further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (dielectric constant k less than  about 3.5) to also reduce the capacitive coupling between adjacent metal lines. One such low k material is spin-on glass, such as un-doped silicon glass (USG) or fluorine-doped silicon glass (FSG), which can be deposited as a gap fill layer in a semiconductor manufacturing process. Another such low k material is silicon carbide which can be used as a dielectric layer in fabricating damascene features.
Conductive materials having a low resistivity include copper and its alloys, which have become the materials of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 xcexcxcexa9-cm compared to 3.1 xcexcxcexa9-cm for aluminum), a higher current and higher carrying capacity. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to etch and pattern precisely. Etching copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory. Therefore, new methods of manufacturing interconnects having copper containing materials and low k dielectric materials are being developed.
Methods for forming vertical and horizontal interconnects include damascene and dual damascene methods. In the damascene method, one or more dielectric materials, such as low k dielectric materials, are deposited and pattern etched to form the vertical interconnects, e.g. vias, or horizontal interconnects, e.g., lines. Conductive materials, such as copper containing materials, and optionally, other materials, such as barrier layer materials used to prevent diffusion of copper containing materials into the surrounding low k dielectric, are then inlaid into the vertical interconnects or the horizontal interconnects. Any excess copper containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, is then removed. In the dual damascene method, both the vertical interconnects and the horizontal interconnects are formed before conductive materials are inlaid.
One method used to form horizontal interconnects includes the use of a hard mask. A hard mask is deposited on a substrate layer, such as a dielectric layer, and patterned to define the openings of horizontal interconnects. Unlike soft masks, hard masks remain as part of the structure after the underlying dielectric layer is etched to form the cavities which are horizontal interconnects. Thus, hard masks should be resistant to the etchant or the process used to etch the underlying dielectric layer. Preferably, hard masks have a low dielectric constant, as they remain in a structure and contribute to the structure""s overall dielectric constant. Furthermore, hard masks are also preferably thermally stable and physically strong, so that they will not be damaged during substrate processing steps, such as annealing at high temperatures and chemical mechanical polishing.
There remains a need for an improved process for depositing hard masks which are strong, have a low dielectric constant, and are resistant to etchants used to etch the dielectric layer upon which they are deposited.
Aspects of the invention generally provide a method for depositing a low k silicon oxycarbide hard mask over a low k dielectric layer. In one embodiment, the invention provides a method of forming an interconnect structure on a substrate surface, comprising depositing a low k dielectric layer comprising a polyimide, a polytetrafluoroethylene, a parylene, a polysilsesquioxane, a fluorinated poly(aryl ether), a fluorinated amorphous carbon, a silicon oxycarbide having a hardness of 1 giga Pascal (gPa) or less, or a silicon carbide, depositing a silicon oxycarbide hard mask having a hardness of greater than 1 gPa over the low k dielectric layer, patterning the hard mask with a horizontal interconnect pattern into the low k dielectric layer to form cavities corresponding to the horizontal interconnect pattern. In another embodiment, the invention provides a method of forming an interconnect structure on a substrate surface, comprising depositing a dielectric layer, depositing an etch stop over the dielectric layer, depositing a low k dielectric layer comprising a polyimide, a polytetrafluroethylene, a parylene, a polysilsesquioxane, a fluorinated poly(aryl ether), a fluorinated amorphous carbon, a silicon oxycarbide having a hardness of 1 giga Pascal (gPa) or less, or a silicon carbide, over the etch stop, and depositing a silicon oxycarbide hard mask having a hardness of greater than 1 gPa and formed by a processing gas comprising a siloxane.
In other aspects of the invention, substrates comprising a low k dielectric layer and a silicon oxycarbide hard mask are provided. In one or more embodiments, a substrate comprises a low k dielectric layer, comprising a material selected from the group consisting of polyimides, polytetrafluroethylene, parylenes, polysilsesquioxanes, fluorinated poly(aryl ethers), fluorinated amorphous carbon, silicon oxycarbides having a hardness of 1 gPa or less, and silicon carbides, and a silicon oxycarbide hard mask having a hardness of greater than 1 gPa and having a porosity of less than about 2%. In one embodiment, a substrate comprises a dielectric layer, an etch stop, a low k dielectric layer comprising a polyimide, a polytetrafluroethylene, a parylene, a polysilsesquioxane, a fluorinated poly(aryl ether), a fluorinated amorphous carbon, a silicon oxycarbide having a hardness of 1 gPa or less, or a silicon carbide, and a silicon oxycarbide hard mask having a hardness of greater than 1 gPa and formed by a processing gas comprising a siloxane. In another embodiment, a substrate comprises a dielectric layer patterned with a horizontal interconnect, an etch stop over the dielectric layer that is not part of the horizontal interconnect, a low k dielectric layer comprising a polyimide, a polytetrafluroethylene, a parylene, a polysilsesquioxane, a fluorinated poly(aryl ether), a fluorinated amorphous carbon, a silicon oxycarbide having a hardness of 1 gPa or less, or a silicon carbide, over the etch stop and patterned with a horizontal interconnect, and a silicon oxycarbide hard mask having a hardness of greater than 1 gPa and formed by a processing gas comprising a siloxane, over the portion of the low k dielectric layer that is not part of the horizontal interconnect.